The present invention relates to a data processing system which includes a burst multiplexor channel (BMC) for transferring command information, data and status information between a host controller and a host memory and more particularly to an improvement in the interface for interfacing the controller to the burst multiplexor channel.
In U.S. Pat. No. 4,403,282 there is disclosed a data processing system having a central processor unit (CPU) and a memory and further including a high speed, or "burst multiplexer", channel for permitting direct access to the memory by an input/output (I/O) device without the need to use registers and control signals from the central processor unit. The high speed channel utilizes its own memory port separate from that of the CPU and includes internal paths for transfering addresses and data between an I/O device and the memory. The channel further includes a memory allocation unit (MAP) which can be loaded by transfer of memory allocation data viz substantially the same common path as the I/O data transfer. Appropriate control logic is also included to control the data and address transfer and the MAP load and dump operations so that blocks of data words can be transferred sequentially and directly to or from the memory.
In data processing systems using a BMC, the BMC (i.e. the BMC board and the associated pair of cables) from the point of view of the controller is a high-speed interface to host memory, and may be used for the transfer of command information, data, or status information between the controller and host memory.
Until now, controllers have used the BMC to transfer command information, data, and status information to and from the host processor's memory. However, since the controller initiates and controls the transfer. it must keep track of the host memory addresses being accessed and the amount of information to be transferred. It thus becomes impractical to interleave packets of one type of information with any other type (e.g. command and data), even through the BMC is perfectly capable of supporting such interleaving.
In intelligent controllers (i.e. controllers incorporating a microprocessor) the data transfer itself is generally accomplished independent of the controller's microprocessor, leaving that microprocessor free for other tasks, such a pre-processing the next command or post-processing the previous one and returning status to the host processor. It is generally necessary for the microprocessor to access the appropriate information in host memory (command or status) in order to complete said processing, but, since the BMC interface is tied up doing the data transfer, this access must be delayed, stalling the microprocessor, wasting valuable processing time, increasing overheads and decreasing performance.